Design Rule Verification Report
Date:
3/24/2016
Time:
5:34:46 PM
Elapsed Time:
00:00:00
Filename:
C:\Users\nrpic_000\Google Drive\PCB Designs\8266 Feather Breakout\Feather Breakout.PcbDoc
Warnings:
0
Rule Violations:
13
Summary
Warnings
Count
Total
0
Rule Violations
Count
Modified Polygon (Allow modified: No), (Allow shelved: No)
0
Net Antennae (Tolerance=0mm) (All)
0
Silk to Silk (Clearance=0.254mm) (All),(All)
0
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
6
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
0
Hole To Hole Clearance (Gap=0.254mm) (All),(All)
0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
7
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
0
Width Constraint (Min=0.254mm) (Max=0.254mm) (Preferred=0.254mm) (All)
0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
0
Clearance Constraint (Gap=0.254mm) (All),(All)
0
Un-Routed Net Constraint ( (All) )
0
Short-Circuit Constraint (Allowed=No) (All),(All)
0
Total
13
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (0.239mm < 0.254mm) Between Track (44.577mm,51.054mm)(44.806mm,51.054mm) on Top Overlay And Pad R3-1(45.847mm,51.054mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.239mm]
Silk To Solder Mask Clearance Constraint: (0.239mm < 0.254mm) Between Track (39.268mm,51.054mm)(39.497mm,51.054mm) on Top Overlay And Pad R3-2(38.227mm,51.054mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.239mm]
Silk To Solder Mask Clearance Constraint: (0.239mm < 0.254mm) Between Track (43.713mm,114.427mm)(43.942mm,114.427mm) on Top Overlay And Pad R2-1(42.672mm,114.427mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.239mm]
Silk To Solder Mask Clearance Constraint: (0.239mm < 0.254mm) Between Track (49.022mm,114.427mm)(49.251mm,114.427mm) on Top Overlay And Pad R2-2(50.292mm,114.427mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.239mm]
Silk To Solder Mask Clearance Constraint: (0.239mm < 0.254mm) Between Track (32.41mm,114.427mm)(32.639mm,114.427mm) on Top Overlay And Pad R1-1(31.369mm,114.427mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.239mm]
Silk To Solder Mask Clearance Constraint: (0.239mm < 0.254mm) Between Track (37.719mm,114.427mm)(37.948mm,114.427mm) on Top Overlay And Pad R1-2(38.989mm,114.427mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.239mm]
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Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Hole Size Constraint: (2.794mm > 2.54mm) Pad U1-A(49.657mm,104.902mm) on Multi-Layer Actual Hole Size = 2.794mm
Hole Size Constraint: (2.794mm > 2.54mm) Pad U1-A(30.607mm,104.902mm) on Multi-Layer Actual Hole Size = 2.794mm
Hole Size Constraint: (2.794mm > 2.54mm) Pad U1-A(30.607mm,59.182mm) on Multi-Layer Actual Hole Size = 2.794mm
Hole Size Constraint: (2.794mm > 2.54mm) Pad U1-A(49.657mm,59.182mm) on Multi-Layer Actual Hole Size = 2.794mm
Hole Size Constraint: (3.2mm > 2.54mm) Pad J1-1(38.303mm,34.369mm) on Multi-Layer Actual Hole Size = 3.2mm
Hole Size Constraint: (3.2mm > 2.54mm) Pad J1-2(38.303mm,28.369mm) on Multi-Layer Actual Hole Size = 3.2mm
Hole Size Constraint: (3.2mm > 2.54mm) Pad J1-3(43.053mm,31.369mm) on Multi-Layer Actual Hole Size = 3.2mm
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